At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This is a unique opportunity to join the fast growing FPGA Prototyping R&D team for S/W development and make a difference. In this role you will help with setting up the infrastructure for QoR measurements, help with debugging hard timing closure problems in the FPGA backend, debug functional issues using world class verification tools and identify and implement strategies for better QoR.
MS Computer Engineering or Computer Science preferred
At least 2 years of experience directly related to role required.
Expert level knowledge of Python or Perl and tcl/tk and Unix scripting is a must.
Proficient Knowledge of R (not just through coursework) is very big plus.
Ideally you have setup software measurement infrastructures, NoSql DBs for data collection along with connections to web backends.
Basic Knowledge about FPGA Flow, FPGA Design Challenges and knowledge of at least one HDL such as Verilog or VHDL and FPGA vendor tools such as Quartus or Vivado is required.
Ability to debug timing closure or QoR issues in FPGAs, analysis of STA reports, etc is very desirable.
Some previous experience in using Agile technologies is preferable.
Prior experience in coding in C/C++ is preferable.