IC Layout Mask Design Engineer

Analog Devices is seeking an IC Layout Mask Design Engineer for our Burlington, VT location.

Responsibilities include but are not limited to:
• IC layout floorplanning.
• Layout Schedule estimation.
• Layout of analog and digital circuits.
• Cell level verification and parasitic extraction using QRC.
• Chip/ Top level routing and interconnect.
• LVS and DRC checks using Assura/ Calibre.
• Tape out/ Steam out/ PG.

Required Skills
The ideal candidate will have the following requirements:
• Associates or Bachelor’s degree in Electrical Engineering or EE Tech minimum.
• 2+ years IC layout experience.
• Familiarity with Cadence tools (Virtuoso Layout XL, Assura).
• Working knowledge of Linux OS.
• Ability to work independently with great attention to detail.
Beneficial Experience would be:
• Experience with Cadence (skill), Unix shell or Perl programming.
• Knowledge of semiconductor device and fabrication principles.
• Analog layout in bipolar, CMOS or BiCMOS technologies.
• Circuit design or analysis experience.

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