As part of our Digital ASIC & FPGA System Architects Team within the Radio Products & Variants organization in Lund you drive and contribute to the definition, systemization, and development of our digital and mix signal ASICs and FPGAs, that are part of Ericsson´s mobile network infrastructure products for the coming 5G network.
As a system Architect, you are actively involved from the early pre-study phase through definition and development of the ASIC/FPGA project until the product has been released. The work is done in close collaboration with colleagues on other sites.
The position requires a solid ASIC/FPGA experience in systemization of advanced SoC, including implementation of signal processing algorithms as well as high-speed interfaces and CPU subsystems. Also, a very good understanding of ASIC technology and design environment is required.
Our organization works in accordance to the Lean and Agile principles with close team interaction.
You will have the chance to work with
• Systemization of ASIC/FPGAs and their blocks and subsystems.
• Support design team during development, verification, and validation of the design.
• Continuously improve and optimize ways of working.
• Generate adequate documentation.
• Master Degree or PhD in Electronic Engineering or equivalent education is preferred.
• Over eight years’ experience in advanced SoC development.
• Good knowledge of ASIC technology.
• Good knowledge of ASIC design environment and design methodology.
• Knowledge of radio access system and their components.
• Knowledge of high speed interfaces, e.i. DDR, CPRI, Ethernet.
• Knowledge in VHDL and/or System Verilog.
• Communication and presentation skills in English are essential.
• Travels may be needed but not required on a frequent basis.
Following experience will be a beneficial asset
• Knowledge about mobile communication standards is an advantage
• Knowledge about several standard interfaces, such as I3C, SPI, SGMII, etc.
• Knowledge of signal processing algorithms and modeling in Matlab or C++.
• Knowledge of embedded CPUs and their IPs.
• Experience from mix-signal systemization, design, and verification.