In this role, the Senior Digital IC Design Verification Engineer will be part of team contributing to Silicon Photonics Solution Group's mission to transform and lead datacenter connectivity and enable Intel's differentiation in the networking space. As Senior Engineer, the individual will be involved in developing key high speed Digital designs from architecture to product. Responsibilities will include - Driving system specifications, defining circuit architectures and enabling designs meeting power, performance and cost for next generation optical interconnects. - As part of the team developing key integrated circuit components the engineer must be able to work collaboratively leading block level development. - Determines creative design approaches and parameters. - Analyzes equipment to establish operating data. - Conducts experimental tests and evaluates results. - Applies and uses independent evaluation to selects components and equipment based on analysis of specifications and reliability. - Evaluates practical capability of vendor to support product development.
Minimum Qualifications: -
MS in Electrical & Electronics Engineering with 4+ years of verification experience- Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development.
Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model, and improve methodology.
Develop testbench, test cases, reference model, coverage model and automation of regression suite.
Run RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage.
Support mixed-signal co-simulation using Verilog models of analog IPSupport product validation, ATE test and QUAL teams during high volume ramp-up
Advanced knowledge of standard ASIC design and verification flows including RTL design, simulation and testbench development
Expertise in HVL and HDL SystemVerilog, Verilog
Advanced knowledge of HVL methodology UVM/OVM
Solid verification skills in problem solving, constrained random testing, and debugging
Experience writing scripts in languages such as Perl or Python
Experience defining coverage space and writing coverage model a plus
Experience with SystemVerilog Assertion SVA a plus