The Mixed Signal IP Solutions Group MIG within the Platform Engineering Group is looking for a PHY Logic Architect. As part of a growing, dynamic new business, the candidate must be successful managing multiple tasks and changing requirements in an innovative environment. The ideal candidate should exhibit behavioral traits that indicate critical and creative thinking, as well as excellent written and verbal communication skills are vital on a small, fast-moving team.
You will be responsible for:
Working on high-speed memory interface designs targeted towards low power optimized implementations.
Micro-architectural definition of memory PHY logic, including JEDEC protocol operation, compensation, power management, training algorithms, and initialization sequences.
Work very closely with the logic design team to implement this functionality in RTL, review and audit validation test plans, and interact with the synthesis team to assist in closing timing.
Bachelor’s Degree in Electrical or Computer Engineering with 9+ years’ experience developing low power designs
Master’s Degree in Electrical or Computer Engineering with 6+ years’ experience developing low power designs
PhD Degree in Electrical or Computer Engineering with 4+ years’ experience developing low power designs
Experience/understanding of analog design concerns and driving to an optimal solution between analog and digital designs
Experience with pre-silicon and post-silicon validation.
Logic design using System Verilog
Architectural specification development, including trade-off analysis and documentation
Low-power design using UPF and clock gating
Multiple clock domain design
State machine design
Simulation and debug experience using VCS/Verdi
Synthesis and speed path debug
Perl / C-shell