UVM verification engineer

Employment Type:
Any
Sector:
Engineering Jobs, IT Jobs
Job Role:
Process Engineering Jobs
Area:
London
Location:
United Kingdom
Salary:
Competitive
Posted:
13-Jul-18
Recruiter:
Mobile Jobs
Job Ref:
PR00100818-X

You will

Exercise your verification skills using the UVM methodology
Plan, design and develop the test environment to be used before the RTL is released
Be responsible for ensuring that the specifications matches the delivered IP
Abilities make possibilities
Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard.

You have

RTL verification experience from testplan to verification closure
A good knowledge of digital design verification techniques and methodologies such as the UVM methodology
Extensive knowledge of the System Verilog language
Hands on experience in developing test benches, tests, sequences, assertions, functional coverage and scoreboards
Some knowledge of the VHDL language would be a plus
You might also have

Experience in RTL Design
Sub-system knowledge related to memory and memory hierarchy
Experience / knowledge of AMBA protocols including AXI4 and ACE
Experience of Verification using FPGAs or emulators
Knowledge of low power design techniques and power aware verification
Experience of Formal verification techniques
Knowledge of scripting languages such as Perl or Python or higher languages such as C, C++ or SystemC

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