As a Microarchitecture Design Engineer, you will be working as a part of the SOC design team within the Scalable performance CPU Development Group, working on next-generation Xeon products/IPs for Server markets.
You will be responsible for all phases of front-end architecture and design. This includes micro-architectural design and specification, working with architects on feature scoping and approvals, feasibility studies, logic design, integration of third party IPs etc.
You will be engaged in activities ranging from uArchitecture development and design trade-off analysis, RTL coding, creating Specification documents, test-plan generation, design reviews, timing analysis, ECOs, and post silicon debug.
Close collaboration with planning teams, architects, validation and physical design teams will be required.
Also, you will provide IP integration support to SoC customers.
You will have at-least a BS or MS degree in Electrical/Computer Engineering, or Computer Science.
Minimum 5 years' experience as a Logic designer.
Additional qualifications include:
Familiarity with Verilog/system Verilog RTL coding, logic design as well as validation/physical design aspects of the work is required.
Familiarity with a range of internal and 3rd-party logic design tools is also required.